ML7000-02 参数 Datasheet PDF下载

¡ Semiconductor

DG

ML7000-01/02/03/ML7001-01/02/03

Ground for the digital signal circuits.

This ground is separate from the analog signal ground AG. The DG pin must be connected to the

AG pin on the printed circuit board to make a common analog ground AG.

PDN

Power down control signal.

A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.

Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from

MSD in a sequential order.

MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK

and XSYNC.

This pin is in a high impedance state except during 8-bit PCM output. It is also in a high

impedance state during power saving or power down mode.

A pull-up resistor must be connected to this pin because its output is configured as an open drain.

This device is compatible with the ITU-T recommendation on coding law and output coding

format.

The ML7000-03 (A-law) and ML7001-03 (A-law) output the character signal, inverting the even

bits.

PCMIN/PCMOUT

Input/Output Level

MSD

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

ML7000-02 (m-law)

ML7001-02 (m-law)

+Full scale

+0

–0

–Full scale

LSD

0

1

1

0

MSD

1

1

0

0

0

1

1

0

1

0

0

1

0

1

1

0

1

0

0

1

0

1

1

0

1

0

0

1

ML7000-03 (A-law)

ML7001-03 (A-law)

LSD

0

1

1

0

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