FEDL6722-05
MSM6722
OKI Semiconductor
Pitch-Control Circuit
[BINARY mode] (P3, P2, P1, P0)
As shown in the diagram below, this IC has an internal prevention circuit for approximately 62
ms of chattering . Therefore, hold these pins at "H" level for 62 ms or more. P3, P2, P1, and P0 pins
are used to directly set the pitch steps.
Sixteen pitch steps are provided, but step 16 cannot be set.
[UP/DOWN mode] (UPC, DWC, PRST)
As shown in the diagram below, this IC has an internal prevention circuit for approximately 62
ms of chattering . Therefore, hold these pins at "H" level for 62 ms or more.
[BINARY mode]
P3
P2
Chattering
Valid
prevention
circuit
To pitch register
data
P1
P0
[UP/DOWN mode]
UPC
Chattering
prevention
circuit
DWC
Pulse
input
To pitch register
PRST
Pitch-Control Circuit
Inputting a "H" level pulse to the UPC pin raises the pitch by one step, and inputting a "H" level
pulse to the DWC pin lowers the pitch by one step. Inputting a "H" level pulse to the PRST pin
or to the UPC and DWC pins at the same time sets the no-pitch change state (pitch step 8).
14/21
OKI [ OKI ELECTRONIC COMPONETS ]
