¡ Semiconductor
MSM7705-01/02/03
DOUT2, DOUT3, DOUT4
PCM signal outputs for channels 2, 3, and 4 when parallel mode is selected.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power-saving state or power-down state.
When the serial mode is selected, this pin is unconnected.
A pull-up resistor must be connected to each of these pins because it is an open drain output.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7705-03 (A-law) outputs the character signal inverting the even bits.
CHPS
Control signal input for the mode selection of PCM input and output.
When this signal is at a logic "1" level, the PCM input and output are in parallel mode. The PCM
data of CH1, CH2, CH3, and CH4 is input to DIN1, DIN2, DIN3, and DIN4 outputs from DOUT1,
DOUT2, DOUT3, and DOUT4 with the same timing.
When this signal is at logic "0" level, the PCM input and output are in serial mode. The PCM data
of CH1 to CH4 is input from DIN4 and output from DOUT1 as time division multiplexed data.
PDN
Power down control signal.
When PDN is at a logic "0" level, both transmit and receive circuits are in power down state.
V
DD
Power supply for +5 V.
A power supply for an analog circuit in the system to which the device is applied should be used.
A bypass capacitor of 0.1
mF
to 1
mF
with excellent high-frequency characteristics and a capacitor
of 10
mF
to 20
mF
should be connected between this pin and the AG pin if needed.
AG
Analog signal ground.
DG
Ground for digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.
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