¡ Semiconductor
MSM7731-01
AGND
This is the analog ground pin.
DGND1, DGND2
These are the digital ground pins.
AV
DD
This is the analog +3 V power supply pin.
DV , DV
DD1
DD2
These are the digital +3 V power supply pins.
SG
Thisistheoutputpinfortheanalogsignalgroundpotential. Theoutputvoltageisapproximately
1.4 V. Insert 10 mF and 0.1 mF ceramic bypass capacitors between the AGND and SG pins. At
power-down reset, this output becomes 0 V.
PDN/RST
This is the power-down reset control input pin. If a logic "0" is input to this pin, the device enters
the power-down state. At this time, all control register bits and internal variables will be reset.
After the power-down reset state is released, the device enters the initial mode (refer to the CR0
control register description). During normal operation, set this pin to a logic "1". Since the
PDN/RST pin is ORed (negative logic) with CR0-B7 of the control register, set the pin to a logic
"1" when controlling power-down reset by the control register.
MCK/X1
This is the master clock input pin. The clock frequency is 19.2 MHz. The input clock may be
asynchronous with respect to the SYNC signal or the BCLK signal. Refer to Figure 2 (a) for an
example application of an external clock and Figure 2 (b) for an example oscillator circuit.
X2
This is the crystal oscillator output pin. If an existing external clock is to be used, leave this pin
open and input the clock to the MCK pin. Refer to Figure 2 (b) for an example oscillator circuit.
MCK/X1
X2
MCK/X1
X2
R
R
C
: T.B.D
: T.B.D
Crystal
Crystal : 19.2 MHz
C
C
Figure 2 (a) External Clock Application
Example
Figure 2 (b) Oscillator Circuit Example
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