¡ Semiconductor
MSM7731-01
SYNC
This is the 8 kHz sync signal I/O pin for digital data communication. This pin is switched to
function as an input or output by the CLKSEL pin. If the internal clock mode is selected by the
CLKSEL pin, an 8 kHz clock synchronized to the BCLK signal is output and digital data
communication is performed. If the external clock mode is selected by the CLKSEL pin, this pin
becomes an input that requires an 8 kHz clock input synchronized to the BCLK pin, and digital
data communication is performed based on this input clock. Fixing this signal to a logic "1" or
logic "0" causes this device to internally write a logic "1" to the PDN/RST (CR0-B7) bit of the
control register, and to enter the power-down reset state. This automatic power-down control
is valid when external clock mode is selected by the CLKSEL pin and automatic power-down
control has been turned ON by the SYPDN (CR11-B0) bit of the control register.
BCLK
This is the shift clock I/O pin for digital data communication. This pin is switched to function
as an input or output by the CLKSEL pin. If the internal clock mode is selected by the CLKSEL
pin, a 64 kHz or 128 kHz clock synchronized to the SYNC signal is output and digital data
communication is performed. Switching between 64 kHz and 128 kHz is performed by the
PCMSEL pin. If m-law PCM is selected by the PCMSEL pin, a 64 kHz clock is output. Or, if 16-
bit linear mode is selected, a 128 kHz clock is output. If the external clock mode is selected by
the CLKSEL pin, this pin becomes an input that requires a clock input synchronized to the
SYNC. In this case, the clock frequency range is from 64 kHz to 2048 kHz.
CLKSEL
This pin selects internal or external clock modes for the SYNC and BCLK signals. A logic "0"
selectstheinternalclockmode. Atthistime, SYNCandBCLKpinsareconfiguredasoutputpins
and each internally generated clock is output to perform digital data communication. A logic
"1" selects the external clock mode and configures the SYNC and BCLK pins as input pins. At
this time, digital data communication is performed with the externally input SYNC and BCLK
clocks. If digital data communication is not used, set this pin to a logic "0" to select internal
clocks. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the
PDN/RST bit (CR0-B7).
PCMI
This is the digital receive signal input pin on the line-side. This input signal is shifted at the
risingedgeoftheBCLKsignalandinput. Thebeginningofdigitaldataisidentifiedontherising
edge of the SYNC signal. The coding format can be selected as m-law PCM or 16-bit linear (2's
complement) by the PCMSEL pin. If the PCMI pin is not used, set it to a logic "1" if m-law PCM
has been selected, or a logic "0" if 16-bit linear mode has been selected. The sync format can be
selected as normal-sync or short-frame-sync by the SYNCSEL pin. Refer to Figure 3 for the
timing. This digital input signal is added internally to the CODEC digital output signal. Be
careful of overflow when using the CODEC.
PCMO
This is the digital transmit signal output pin on the line-side. This output signal is synchronized
to the rising edge of the BCLK and SYNC signals and then output. When not used for output,
this pin is in the high impedance state. It is also at high impedance during the power-down reset
and the initial modes. The coding format can be selected as m-law PCM or 16-bit linear (2's
complement) by the PCMSEL pin. The sync format can be selected as normal-sync or short-
frame-sync by the SYNCSEL pin. Refer to Figure 3 for the timing.
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