FEDL9225B-03
Semiconductor
1
MSM9225B
BLOCK DIAGRAM
CS
A7-0
AD7-0/D7-0
PALE
PWR
PRD
/SR
W
PRDY/SWAIT
8
8
Parallel I/F
Bit timing logic (BTL)
microcontroller interface
Bit stream
logic
(BSL)
RD
RDY
RW
WAIT
Transmission
control logic
(TCL)
Message
memory
Control
register
Data
manage-
ment
logic
Tx0
Tx1
SCLK
SDI
SDO
INT
Mode1, 0
XT
XT
RESET
Serial I/F
Error
management
logic (EML)
Timing
generator
Receive
control logic
(RCL)
Rx0
Rx1
V
DD
GND
CONFIGURATION EXAMPLE
ABS
CAN
Engine
controller
Power steering
CAN
Seat-position controller
Suspension
CAN
CAN
CAN Bus
CAN
CAN
Transmission
CAN
Automatic
air conditioner
CAN
CAN
Power window
Outside mirror controller
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