FEDL9225B-03
Semiconductor
1
MSM9225B
Symbol
Pin
Type
Description
Microcontroller interface select pins
Mode1
0
0
1
1
Mode0
0
1
0
1
Interface
Separate No address latch signal
buses
With address latch signal
Multiplexed buses
Serial mode
Parallel
mode
Mode1, 0
29, 30
I
INT
11
O
Interrupt request output pin
When an interrupt request occurs, a “L” level is output. This pin
automatically outputs a “H” level after 32 Ts (T = 1/fosc).
Three types of interrupts share this pin: transmission complete, reception
complete, and error.
Reset pin
System is reset when this pin is at a “L” level.
Clock pins. If internal oscillator is used, connect a crystal (ceramic
resonator).
If external clock is used, input clock via XT pin. The
XT
pin should be left
open.
Receive input pin.
Power supply pin
GND pin
Differential amplifier included.
Transmission output pin
RESET
XT
XT
Rx0, Rx1
Tx0, Tx1
V
DD
GND
25
13
14
18, 19
22, 23
12, 20, 24, 40
6, 15, 17, 21,
28, 39
I
I
O
I
O
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