欢迎访问ic37.com |
会员登录 免费注册
发布采购

OX12PCI840-PQC60-A 参数 Datasheet PDF下载

OX12PCI840-PQC60-A图片预览
型号: OX12PCI840-PQC60-A
PDF下载: 下载PDF文件 查看货源
内容描述: 集成并行端口和PCI接口 [Integrated Parallel Port and PCI interface]
分类和应用: PC
文件页数/大小: 33 页 / 272 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
 浏览型号OX12PCI840-PQC60-A的Datasheet PDF文件第3页浏览型号OX12PCI840-PQC60-A的Datasheet PDF文件第4页浏览型号OX12PCI840-PQC60-A的Datasheet PDF文件第5页浏览型号OX12PCI840-PQC60-A的Datasheet PDF文件第6页浏览型号OX12PCI840-PQC60-A的Datasheet PDF文件第8页浏览型号OX12PCI840-PQC60-A的Datasheet PDF文件第9页浏览型号OX12PCI840-PQC60-A的Datasheet PDF文件第10页浏览型号OX12PCI840-PQC60-A的Datasheet PDF文件第11页  
OXFORD SEMICONDUCTOR LTD.
OX12PCI840
Pin Numbers
Dir
1
Name
Description
Multi-purpose & External interrupt pins
82, 51
I/O
EEPROM pins
81
78
80
79
Miscellaneous pins
77
Power and ground
2
8,30,40,56,97
16,45,67,87
3,7,20,29,35,41,48,55,61,72,92,96
15,44,66,85
O
O
IU
O
I
V
V
G
G
MIO[1:0]
Multi-purpose I/O pins. Can drive high or low, or assert a PCI
interrupt
EEPROM clock
EEPROM active-high Chip Select
EEPROM data in. When the serial EEPROM is connected,
this pin should be pulled up using 1-10k resistor. When the
EEPROM is not used the internal pull-up is sufficient.
EEPROM data out.
Test Pin : should be held low at all times
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
Supplies GND to output buffers in switching (AC) state
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
EE_CK
EE_CS
EE_DI
EE_DO
TEST
AC VDD
DC VDD
AC GND
DC GND
Table 1: Pin Descriptions
Note 1: Direction key:
I
ID
O
I/O
OD
NC
Z
Input
Input with internal pull-down
Output
Bi-directional
Open drain
No connect
High impedance
P_I
P_O
P_I/O
P_OD
G
V
PCI input
PCI output
PCI bi-directional
PCI open drain
Ground
5.0V power
Note 2: Power & Ground
There are two GND and two VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail).
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation from the chip. Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI and Local Bus
pins.
DS-0021 Jun 05
Page 7