OXFORD SEMICONDUCTOR LTD.
OX16C950 rev B
6
R
EGISTER
D
ESCRIPTION
T
ABLES
The three address lines select the various registers in the UART. Since there are more than 8 registers, selection of the registers
is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1. LCR[7]=1 enables the divider latch registers DLL and DLM.
2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
3. ACR[7]=1 enables access to the 950 specific registers.
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 17.
Register
Name
THR
1
RHR
1
IER
1,2
650/950
Mode
550/750
Mode
FCR
3
650 mode
750 mode
950 mode
ISR
3
LCR
4
Address
000
000
R/W
W
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data to be transmitted
Data received
CTS
interrupt
mask
Special
Char.
Detect
Sleep
mode
Alternate
Unused
sleep
mode
RHR Trigger
THR Trigger
Level
Level
RHR Trigger
FIFO
Unused
Level
Size
Unused
FIFOs
enabled
Divisor
latch
access
Tx
break
Interrupt priority
(Enhanced mode)
Force
parity
CTS &
RTS
Flow
Control
XON-Any
THR
Empty
Odd /
even
parity
Internal
Loop
Back
Enable
Rx
Break
Parity
enable
RTS
interrupt
mask
Modem
interrupt
mask
DMA
Mode /
Tx
Trigger
Enable
Rx Stat
interrupt
mask
THRE
interrupt
mask
RxRDY
interrupt
mask
001
R/W
010
W
Flush
THR
Flush
RHR
Enable
FIFO
010
011
R
R/W
Interrupt priority
(All modes)
Number
of stop
bits
Interrupt
pending
Data length
MCR
3,4
550/750
Mode
650/950
Mode
LSR
3,5
Normal
9-bit data
mode
MSR
3
Unused
100
R/W
Baud
prescale
101
R
Data
Error
IrDA
mode
Tx Empty
OUT2
(Int En)
OUT1
RTS
DTR
Framing
Error
Parity
Error
Overrun
Error
RxRDY
110
R
DCD
RI
SPR
3
Normal
111
R/W
9-bit data
Unused
mode
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
DLL
DLM
000
001
R/W
R/W
Divisor latch bits [7:0] (Least significant byte)
Divisor latch bits [15:8] (Most significant byte)
9
th
Rx
data bit
Delta
Trailing
DSR
CTS
DCD
RI edge
Temporary data storage register and
Indexed control register offset value bits
Delta
DSR
Delta
CTS
9
th
Tx
data bit
Table 4: Standard 550 Compatible Registers
Data Sheet Revision 1.2
Page 15
OXFORD [ OXFORD SEMICONDUCTOR ]
