OXFORD SEMICONDUCTOR LTD.
OXmPCI954
2
OX
M
PCI954 D
EVICE
M
ODES
The OXmPCI954 supports several modes of operation.
3 modes of the device are (software)
backwards compatible
with the OX16PCI954 device. There are a further 3 modes that are
enhanced
modes, which offer additional features over those available in the
backwards compatible
modes. Then, there is a
standalone mode
that allows a synchronous local bus access to the internal UARTs, without any form of PCI transactions. These
modes are summarized in the following table.
Device Mode
000
001
010
011
100
101
110
111
Mode Pin Selection
MODE(2:0) = 000
MODE(2:0) = 001
MODE(2:0) = 010
MODE(2:0) = 011
MODE(2:0) = 100
MODE(2:0) = 101
MODE(2:0) = 110
MODE(2:0) = 111
Functionality
Function 0
:
QUAD Uarts
Function 1
:
8-bit Local Bus
Function 0
:
QUAD Uarts
Function 1
:
Parallel Port
Function 0
:
QUAD Uarts
Subsys ID/Subsys Vendor ID via Device Pins
Function 0
:
QUAD Uarts (Unique BARs)
Function 1
:
8-bit Local Bus
Function 0
:
QUAD Uarts
Function 1
:
8-bit Local Bus
Function 0
:
QUAD Uarts
Function 1
:
Parallel Port
TestMode (Reserved).
Standalone Mode
Backwards Compatible /
Enhanced Modes
Backwards Compatible*
Backwards Compatible*
Backwards Compatible*
Enhanced Mode
Enhanced Mode
Enhanced Mode
N/A
N/A
* The OXmPCI954 is not a direct ‘drop-in’ replacement part for the OX16PCI954 owing to a small pinout change and voltage.
The device is only S/W compatible.
In the
Enhanced Modes,
the following additional features are made available over the underlying functionality of the device.
•
•
•
•
•
•
•
Pin 88/M15 (MIO[11]) is re-defined as a
PCI/miniPCI Mode Selection Pin.
Functionality normally associated with the pin MIO[11] is no longer available. This results in the pins MIO[10:0] serving as
Multi-purpose I/O pins.
All Function 0 and Function 1 interrupts assert on the INTA# pin (by
default).
Local Registers provide additional Controls and Status Indication.
Function 0 option to allow each UART to be separately addressable via its own Base Address Register (in I/O Space)
This option can be exercised by the device pins (MODE 011) or by using the external EEPROM to set a specified field in the
local registers.
Function 0 and Function 1 Power Management Registers indicate Compatibility to Power Management Specification 1.1
Each function implements Power Management Data/Data Scale fields,
returning user defined data.
Availability of 2 Additional EEPROM Zones : The
Power Management Data
Zone and The
Function Access
Zone.
Specifically for
MiniPCI Selection (Pin 88/M15 = ‘1’ in Enhanced Modes)
•
Device pin INTB#’ is re-defined as a CLKRUN# pin. Compliant to PCI Mobile Design Guide revision 1.1
For PCI modes (Pin 88/M15 = ‘0’ in Enhanced Modes) INTB# is an unused PCI interrupt line.
•
Device supports PME# generation from the D3cold state and preserves PME# context. This is compliant to Mini
PCI Specification, revision 1.0
DS-0019 Jun 05
External—Free Release
Page 8
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