OXFORD SEMICONDUCTOR LTD.
OXmPCI954
3
B
LOCK
D
IAGRAM
MODE[2:0]
FIFOSEL
MIO[11]*
Config.
Interface
SOUT{3:0]
SIN[3:0]
* MIO[11] is a mode selection pin, in the Enhanced Mode.
Function 0
Quad
UARTs
RTS[3:0]
DTR{3:0]
CTS{3:0]
DSR{3:0]
AD[31:0]
C/BE[3:0]#
Interface Data / Control Bus
DCD{3:0]
RI{3:0]
PCI_CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RESET#
INTA#
INTB#/CLKRUN#
PME#
PCI
(miniPCI)
Interface
Interrupt
Logic
MIO Pins
MIO[11:0]*
PD[7:0]
ACK#
PE
BUSY
Parallel Port
SLCT
ERR#
SLIN#
INIT#
AFD#
XTLI
XTLO
Clock &
Baud Rate
Generator
STB#
Function 1
UART_Clk_Out
Local_Bus Clk
LBA7:0]
LBCS[3:0]
LBD[7:0]
Local Bus
LBWR#
EE_DI
EEPROM
Interface
EE_CS
EE_CK
EE_DO
LBRD#
LBRST
DATA_DIR
OXmPCI954 Block Diagram
DS-0019 Jun 05
External—Free Release
Page 9