Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FEATURES
•
Wide supply voltage range from 1.65 V to 5.5 V
•
High noise immunity
•
Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ±24
mA output drive (V
CC
= 3.0 V)
•
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
•
CMOS low power consumption
•
Latch-up performance exceeds 250 mA
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5 V
•
Multiple package options
•
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay CP to Q
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
Ω
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
maximum frequency
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
DESCRIPTION
74LVC1G80
The 74LVC1G80 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This
feature allows the use of this device in a mixed
3.3 V and 5 V environment.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G80 provides a single positive-edge triggered
D-type flip-flop.
Information on the data input is transferred to the Q output
pin on the LOW-to-HIGH transition of the clock pulse.
The input pin D must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
TYPICAL
3.4
2.3
2.5
2.4
1.8
350
5.0
17
UNIT
ns
ns
ns
ns
ns
MHz
pF
pF
2004 Sep 10
2
PANASONIC [ PANASONIC SEMICONDUCTOR ]
