Philips Semiconductors
Product specification
Dual inverter
74LVC2G04
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant input/output for interfacing with 5 V logic
• High noise immunity
The 74LVC2G04 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices.
These feature allows the use of these devices as
translators in a mixed 3.3 V and 5 V environment.
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
– JESD8B/JESD36 (2.7 V to 3.6 V).
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Multiple package options
The 74LVC2G04 provides two inverting buffers.
• Specified from −40 °C to +85 °C and
−40 °C to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
ns
tPHL/tPLH
propagation delay inputs nA to
outputs nY
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
3.5
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.2
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.7
ns
ns
ns
ns
pF
pF
V
CC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.7
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.9
CI
input capacitance
2.5
CPD
power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2
13.5
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC
.
2004 Sep 15
2