PE9704
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
17
Pin Name
GND
CLOCK
Interface Mode
Both
Serial
Direct
Direct
Direct
Direct
Both
Both
Serial
Direct
Direct
Direct
Both
Both
Both
Type
Ground
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Description
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of
CLOCK.
M Counter bit6
M Counter bit7
M Counter bit8 (MSB)
A Counter bit0
Selects direct interface mode (D
MODE
=1) or serial interface mode (D
MODE
=0)
Same as pin 1
Enhancement register write enable. While E_WR is “high”, DATA can be serially
clocked into the enhancement register on the rising edge of CLOCK.
A Counter bit1.
A Counter bit2
A Counter bit3 (MSB)
RF prescaler input from the VCO. 3.0 GHz maximum frequency.
Ground.
Ground.
No connect.
18
M
6
19
20
21
22
23
M
7
M
8
A
0
D
MODE
V
DD
E_WR
24
A
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Note 1:
Note 2:
A
2
A
3
F
IN
GND
GND
N/C
V
DD
D
OUT
V
DD
N/C
GND
PD_D
PD_U
V
DD
C
EXT
GND
GND
F
R
ENH
LD
Both
Both
Both
Both
Both
Both
Both
Both
Both
Serial
Input
Output, OD
Output
(Note 1)
Output
Output
Both
Serial
Both
(Note 1)
Output
(Note 1)
Same as pin 1
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to D
OUT
through enhancement register programming.
Same as pin 1
No connect.
Ground.
PD_D pulses down when f
p
leads f
c
.
PD_U pulses down when f
c
leads f
p
.
Same as pin 1
Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 kΩ series
resistor. Connecting C
EXT
to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Ground
Ground
Reference frequency input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Lock detect output, the open-drain logical inversion of C
EXT
. When the loop is
locked, LD is high impedance; otherwise LD is a logic low (“0”).
V
DD
pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
All digital input pins have 70 kΩ pull-down resistors to ground.
Document No. 70-0083-03
│
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