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9704-01 参数 Datasheet PDF下载

9704-01图片预览
型号: 9704-01
PDF下载: 下载PDF文件 查看货源
内容描述: 3000兆赫的UltraCMOS ?整数N分频PLL抗辐射的空间应用 [3000 MHz UltraCMOS⑩ Integer-N PLL Rad Hard for Space Applications]
分类和应用:
文件页数/大小: 10 页 / 246 K
品牌: PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
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PE9704
Product Specification
Figure 4. Serial Interface Mode Timing Diagram
DATA
E_WR
t
EC
t
CE
CLOCK
S_WR
t
DSU
t
DHLD
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
Enhancement Register
The functions of the enhancement register bits are shown below. All bits are active high. Operation is
undefined if more than one output is sent to D
OUT
.
Table 9. Enhancement Register Bit Functionality
Bit Function
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
** Program to 0
Reserved**
Reserved**
f
p
output
Power down
Counter load
MSEL output
f
c
output
PB
Drives the M counter output onto the D
OUT
output.
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the D
OUT
output.
Drives the R counter output onto the D
OUT
output
Allows Fin to bypass the 10/11 prescaler
Description
Phase Detector Outputs
The phase detector is triggered by rising edges
from the main counter (f
p
) and the reference
counter (f
c
). It has two outputs,
PD_U,
and
PD_D.
If the divided VCO leads the divided reference in
phase or frequency (f
p
leads f
c
),
PD_D
pulses
“low”. If the divided reference leads the divided
VCO in phase or frequency (f
c
leads f
p
),
PD_U
pulses “low”. The width of either pulse is directly
proportional to phase offset between the two input
signals, f
p
and f
c
. The phase detector gain is
430 mV / radian.
PD_U and PD_D
are designed to drive an active
loop filter which controls the VCO tune voltage.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 10
PD_U
pulses result in an increase in VCO
frequency and
PD_D
results in a decrease in VCO
frequency.
Software tools for designing the active loop filter
can be found at Peregrine’s web site:
www.psemi.com
Lock Detect Output
A lock detect signal is provided at pin LD, via the
pin C
EXT
(see Figure 1). C
EXT
is the logical “NAND”
of PD_U and PD_D waveforms, driven through a
series 2 kΩ resistor. Connecting C
EXT
to an
external shunt capacitor provides integration of
this signal.
Document No. 70-0083-03
UltraCMOS™ RFIC Solutions