PE9763
Product Specification
Pin No.
Pin
Name
V
DD
Valid
Mode
Type
(Note 1)
(Note 1)
ESD V
DD
.
Prescaler V
DD
.
Description
46
V
DD
47
48
F
in
F
in
Both
GND
49
GND
GND
50
CEXT
Downbond
Downbond
Downbond
Output
Both
Input
Input
Prescaler input from the VCO. 3.2 GHz max frequency.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 W resistor directly to the ground plane.
Prescaler ground.
Prescaler ground.
Output driver/charge pump ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kW series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Data out function, enabled in enhancement mode.
Output driver/charge pump V
DD
.
Output driver/charge pump ground.
PD_D pulses down when f
p
leads f
c
. PD_U is driven to GND when CPSEL = “High”.
Charge pump output. Selected when CPSEL = “1”. Tristate when CPSEL = “Low”.
PD_U pulses down when f
c
leads f
p
. PD_D is driven to GND when CPSEL = “High”.
Output driver/charge pump ground.
Output driver/charge pump V
DD
.
Phase detector GND.
Phase detector V
DD
.
ESD V
DD
.
ESD ground.
Reference ground.
Reference frequency input.
Reference V
DD
.
Digital core V
DD
.
Digital core ground.
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
Charge pump select. “High” enables the charge pump and disables pins PD_U and PD_D by
forcing them “low”. A “low” Tri-states the CP and enables PD_U and PD_D.
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 2
19
.
Both
Both
Both
51
52
53
54
55
56
57
58
59
LD
D
OUT
V
DD
GND
PD_D
CP
PD_U
GND
V
DD
GND
V
DD
Output
Output
(Note 1)
Downbond
Both
Both
Both
Output
Output
Output
Downbond
(Note 1)
Downbond
(Note 1)
(Note 1)
Downbond
Downbond
60
V
DD
GND
61
GND
62
63
64
f
r
V
DD
V
DD
GND
65
66
67
68
Note 1:
Note 2:
ENH
CPSEL
MS2_SEL
RND_SEL
Both
Both
Both
Both
Input
(Note 1)
(Note 1)
Downbond
Input
Input
Input
Input
Both
All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
All digital input pins have 70 kΩ pull-down resistors to ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0140-01
│
UltraCMOS™ RFIC Solutions
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
