PE9763
Product Specification
Table 6. AC Characteristics
V
DD
= 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
F
in
P
Fin
F
in
P
Fin
f
r
P
fr
f
c
Φ
N
Φ
N
Note 1:
Note 2:
Note 3:
Note 4:
Parameter
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata set-up time to Sclk rising edge
Sdata hold time after Sclk rising edge
S_WR pulse width
Sclk rising edge to S_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge
E_WR transition to Sclk rising edge
Conditions
Control Interface and Latches (see Figures 3, 4)
(Note 1)
Min
Typ
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
10
10
30
30
30
30
30
275
External AC coupling
-5
50
External AC coupling
Reference Divider
(Note 3)
Single ended input
Phase Detector
(Note 3)
1 kHz Offset
10 kHz Offset
-88
-92
-2
50
-5
3200
5
300
5
100
Main Divider (Including Prescaler) (Note 4)
Operating frequency
Input level range
Operating frequency
Input level range
Operating frequency
Reference input power (Note 2)
Comparison frequency
Phase Noise
Phase Noise
Main Divider (Prescaler Bypassed) (Note 4)
MHz
dBm
MHz
dBm
MHz
dBc/Hz
dBc/Hz
MHz
dBm
SSB Phase Noise (F
in
= 1.9 GHz, f
r
= 20 MHz, f
c
= 10 MHz, LBW = 50 kHz, V
DD
= 3.0 V, Temp = 25° C
)
(Note 4)
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Parameter below are not tested for die sales. These parameters are verified during the element evaluation per the die flow.
Document No. 70-0140-01
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