PE9601
Product Specification
Main Counter Chain
The main counter chain divides the RF input
frequency, F
in
, by an integer derived from the user
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9 bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows F
in
to bypass the prescaler and
powers down the prescaler.
The output from the main counter chain, f
p
, is related
to the VCO frequency, F
in
, by the following equation:
f
p
= F
in
/ [10 x (M + 1) + A]
where A
≤
M + 1, M ¹ 0
When the loop is locked, F
in
is related to the
reference frequency, f
r
, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
where A
≤
M + 1, M ¹ 0
(2)
(1)
Parallel input data, D[7:0], are latched in a parallel
fashion into one of three, 8-bit primary register
sections on the rising edge of M1_WR, M2_WR, or
A_WR per the mapping shown in Table 7 on page
10. The contents of the primary register are
transferred into a secondary register on the rising
edge of Hop_WR according to the timing diagram
shown in Figure 6. Data are transferred to the
counters as shown in Table 7 on page 10.
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This double
buffering for “ping-pong” counter control is
programmed via the FSELP input. When FSELP is
“high”, the primary register contents set the counter
inputs. When FSELP is “low”, the secondary register
contents are utilized.
The FSELP input is synchronized with the loading of
the counters in order to minimize glitches in the
“ping-pong” case. Due to this attribute, applications
using a single register should use the secondary
register (i.e. tie FSELP “low”) to avoid problems with
the prescaler powering up in the disabled state.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of E_WR
according to the timing diagram shown in Figure 6.
This data provides control bits as shown in Table 8
on page 10 with bit functionality enabled by
asserting the Enh input “low”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode
input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M
7
and M
8
, and R Counter inputs R
4
and R
5
are internally forced low (“0”)
Serial Interface Mode
Serial Interface Mode is selected by setting the
Bmode input “low” and the Smode input “high”.
While the E_WR input is “low” and the S_WR input
is “low”, serial input data (Sdata input), B
0
to B
19
, are
clocked serially into the primary register on the rising
edge of Sclk, MSB (B
0
) first. The contents from the
primary register are transferred into the secondary
register on the rising edge of either S_WR or
Hop_WR according to the timing diagram shown in
Figure 6 and Figure 7. Data are transferred to the
counters as shown in Table 7 on page 10.
A consequence of the upper limit on A is that F
in
must be greater than or equal to 90 x (f
r
/ (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in a
minimum M Counter divide ratio of “2”.
In Direct Interface Mode, main counter inputs M
7
and
M
8
are internally forced low.
Reference Counter
The reference counter chain divides the reference
frequency, f
r
, down to the phase detector
comparison frequency, f
c
.
The output frequency of the 6 bit R Counter is
related to the reference frequency by the following
equation:
f
c
= f
r
/ (R + 1)
where R > 0
(3)
Note that programming R equal to “0” will pass the
reference frequency, f
r
, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R
4
and R
5
are internally forced low (“0”).
Register Programming
Parallel Interface Mode
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
Document No. 70-0025-05
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 14
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