PE9701 参数 Datasheet PDF下载

PE9701

Product Specification

Table 1. Pin Descriptions (continued)

Pin No.

31

32

33

34

35

36

37

38

39

40

41

42

43

44

Note 1:

Pin Name

V

DD

-f

p

Dout

V

DD

Cext

V

DD

CP

NC

V

DD

-f

c

f

c

GND

GND

f

r

LD

Enh

Interface Mode

ALL

Serial, Parallel

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

Serial, Parallel

Type

(Note 1)

Output

(Note 1)

Output

(Note 1)

Output

V

DD

for f

p

Description

Data Out. The MSEL signal and the raw prescaler output are available on Dout

through enhancement register programming.

Same as pin 1.

Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.

Connecting Cext to an external capacitor will low pass filter the input to the inverting

amplifier used for driving LD.

Same as pin 1.

Charge pump current is sourced for “up” when f

c

leads f

p

and sinked for “down”

when f

c

lags f

p

.

No connection.

(Note 1)

Output

V

DD

for f

c

Monitor pin for reference divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding V

DD

pin 38.

Ground.

Ground.

Input

Output,

OD

Input

Reference frequency input.

Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is

high impedance, otherwise LD is a logic low (“0”).

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

V

DD

pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.

V

DD

pins 31 and 38 are used to enable test modes and should be left floating.

Note 2:

All digital input pins have 70 kΩ pull-down resistors to ground.

©2003-2006 Peregrine Semiconductor Corp. All rights reserved.

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Document No. 70-0035-02

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