PE9701
Product Specification
Table 6. AC Characteristics:
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 4, 5, 6)
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
t
MDO
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata hold time after Sclk rising edge, D[7:0] set-up time to
M1_WR, M2_WR, A_WR, E_WR rising edge
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
E_WR transition to Sclk rising edge
MSEL data out delay after Fin rising edge
C
L
= 12 pf
(Note 1)
30
30
10
10
30
30
30
30
30
8
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main Divider (Prescaler Enabled)
F
in
P
Fin
Operating frequency
Input level range
External AC coupling
500
-5
3000
5
MHz
dBm
Main Divider (Prescaler Bypassed)
F
in
P
Fin
Operating frequency
Input level range
External AC coupling
50
-5
300
5
MHz
dBm
Reference Divider
f
r
P
fr
Phase Detector
f
c
Note 1:
Note 2:
Note 3:
Comparison frequency
(Note 3)
20
MHz
Operating frequency
Reference input power (Note 2)
(Note 3)
Single-ended input
-2
100
MHz
dBm
Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 V
p-p
.
Parameter is guaranteed through characterization only, and is not tested.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 13
Document No. 70-0035-02
│
UltraCMOS™ RFIC Solutions
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