PI5A4684
Chip Scale Packaging,
Dual SPDT Analog Switch
Test Circuits and Timing Diagrams
V
CC
V
CC
COM
R
L
IN
LOGIC
INPUT
GND
C
L
V
N
NC
or NO
V
OUT
50Ω
35pF
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
Notes:
1. Unused input (NC or NO) must be grounded.
Figure 1. AC Test Circuit
Logic
Input
V
IH
V
IL
Off
50% On
V
OUT
Off
t
OFF
90%
t
ON
Logic Input Waveforms inverted for
Switches that have opposite logic
* 1.5V for 3.3V Supply
90%
t
r
< 5ns
t
f
< 5ns
Switch
Output
0V
Figure 2. AC Waveforms
V
IN
NC
NO
COM
R
L
C
L
V
OUT
50Ω
35pF
Logic
Input
V
OUT
50%
IN
Logic
Input
0.9 x V
OUT
t
BBM
Figure 3. Break Before Make Interval Timing
06-0062
5
PS8792B
05/09/06