PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
AC Specifications
Parameter
ten
tdis
tjit(cc+)
tjit(cc-)
t(Ø)
t(Ø)dyn
tsk(o)
tjit(per)
tjit(hper)
slr(i)
slr(o)
V
OX
OE to and Y/Y
OE to and Y/Y
Cycle-to-cycle jitter
Static phase offset
(11)
Dynamic phase offset
Output clock skew
Period jitter
(12)
Halk period jitter
(12)
Input clock slew rate
Output enable (OE)
Output clock slew rate
(14, 16)
Outpu differenital-pair cross voltage
(13)
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)
(15)
Description
Diagram
see Fig 11
see Fig 11
see Fig 4
see Fig 5
see Fig 10
see Fig 6
see Fig 7
see Fig 8
see Fig 9
see Fig 9
see Fig 1, 9
see Fig 2
-40
-75
1
0.5
1.5
(V
DDQ
/2)
-0.1
2.5
3
(V
DDQ
/2)
+0.1
V
2.5
0
0
-50
-50
AV
DD
, V
DDQ
= 1.8V ±0.1V
Min.
Nom.
Max.
8
8
40
-40
50
50
40
40
75
4
V/ns
ps
Units
ns
The PLL on the PI6CU877 is capable of meeting all the above test parameters while supporting SSC synthesirers
with the following parameters:
SSC modulation frequency
SSC clock input frequency deviation
PLL Loop Bandwidth
30.00
0.00
2.0
33
-0.50
kHz
%
MHz
PI6CU877 PLL design should target the values below to minimize the SCC induced skew:
Notes:
11. Static Phase Offset does not include Jitter
12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
13. VOX specified at the DRAM clock input or the test load.
14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these
Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered
DDR2 DIMM application.
15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differen-
tial-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used.
16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended.
6
PS8689B
08/05/04
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
