PI7C21P100B
2-PORT PCI-X TO PCI-X BRIDGE
4
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C21P100B, and transaction termination. The PI7C21P100B has two 2KB buffers for read
data buffering of upstream and downstream transactions. Also, PI7C21P100B has two 1KB
buffers for write data buffering of upstream and downstream transactions.
4.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI and PCI-X transactions performed by PI7C21P100B.
and Target columns indicate support for each transaction when PI7C21P100B initiates
transactions as a master, on the primary and secondary buses, and when PI7C21P100B
responds to transactions as a target, on the primary and secondary buses.
Table 4-1 PCI AND PCI-X TRANSACTIONS
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Responds as Target
Primary
Secondary
N
N
N
N
Y
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
N
N
N
N
Y
Y (Type 0 only)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
As indicated in Table 4-1, the following commands are not supported by PI7C21P100B:
PI7C21P100B never initiates a transaction with a reserved command code and, as a
target, PI7C21P100B ignores reserved command codes.
PI7C21P100B does not generate interrupt acknowledge transactions. PI7C21P100B
ignores interrupt acknowledge transactions as a target.
PI7C21P100B does not respond to special cycle transactions. PI7C21P100B cannot
guarantee delivery of a special cycle transaction to downstream buses because of the
broadcast nature of the special cycle command and the inability to control the transaction as a
target. To generate special cycle transactions on other buses, either upstream or downstream,
Type 1 configuration write must be used.
Page 22 of 79
November 2005 – Revision 1.02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
