PI7C21P100B
2-PORT PCI-X TO PCI-X BRIDGE
8
CONFIGURATION REGISTERS
PCI configuration defines a 64 DWORD space to define various attributes of PI7C21P100B.
8.1
CONFIGURATION REGISTER SPACE MAP
Table 8-1 CONFIGURATION SPACE MAP
Bit Number
31 – 24
Device ID
Primary Status
23 – 16
15 – 8
7-0
Vendor ID
Primary Command
Class Code
Revision ID
BIST
Header Type
Primary Latency Timer
Cache Line Size
Lower Memory Base Address
Upper Memory Base Address
Secondary Latency
Subordinate Bus
Secondary Bus Number
Primary Bus Number
Timer
Number
Secondary Status
I/O Limit
I/O Base
Memory Limit
Memory Base
Prefetchable Memory Limit
Prefetchable Memory Base
Prefetchable Base Upper 32-bit
Prefetchable Limit Upper 32-bit
I/O Limit Upper 16-bit
I/O Base Upper 16-bit
Reserved
Capability Pointer
Expansion ROM Base Address
Bridge Control
Interrupt Pin
Interrupt Line
Secondary Data Buffering Control
Primary Data Buffering Control
Reserved
Miscellaneous Control
Reserverd
Extended Chip Control
Extended Chip Control
2
1
Reserved
Reserved
Arbiter Mode
Reserved
Arbiter Enable
Reserved
Arbiter Priority
Reserved
SERR# Disable
Primary Retry Counter
Secondary Retry Counter
Reserved
Discard Timer Control
Reserved
Retry and Timer Status
Reserved
Opaque Memory
Enable
Opaque Memory Limit
Opaque Memory Base
Opaque Memory Base Upper 32-bit
Opaque Memory Limit Upper 32-bit
PCI-X Secondary Status
Next Capability Pointer
PCI-X Capability ID
PCI-X Bridge Status
Secondary Bus Upstream Split Transaction
Primary Bus Downstream Split Transaction
Power Management Capabilities
Next Capabilities
Power Management ID
Pointer
PCI-to-PCI Bridge Support Extension
Power Management Control and Status
Reserved
Secondary Bus Private Device Mask
Reserved
Reserved
Miscellaneous Control 2
Reserved
DWORD
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
80h
84h
88h
8Ch
90h
94h
98h-Ach
B0h
B4h
B8h
BCh-FFh
Page 42 of 79
November 2005 – Revision 1.02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
