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PI7C21P100BNH 参数 Datasheet PDF下载

PI7C21P100BNH图片预览
型号: PI7C21P100BNH
PDF下载: 下载PDF文件 查看货源
内容描述: 双端口PCI - X到PCI - X桥接 [2-PORT PCI-X TO PCI-X BRIDGE]
分类和应用: 总线控制器微控制器和处理器外围集成电路PC时钟
文件页数/大小: 79 页 / 975 K
品牌: PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
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PI7C21P100B
2-PORT PCI-X TO PCI-X BRIDGE
8.1.1
SIGNAL TYPE DEFINITION
SIGNAL TYPE
RO
RW
RWC
DEFINITION
READ ONLY
READ / WRITE
READ / WRITE 1 TO CLEAR
8.1.2
VENDOR ID REGISTER – OFFSET 00h
BIT
15:0
FUNCTION
Vendor ID
TYPE
RO
DESCRIPTION
Identifies Pericom as the vendor of this device. Hardwired as 12D8h
8.1.3
DEVICE ID REGISTER – OFFSET 00h
BIT
31:16
FUNCTION
Device ID
TYPE
RO
DESCRIPTION
Identifies the device as PI7C21P100B. Hardwired as 01A7h.
8.1.4
COMMAND REGISTER – OFFSET 04h
BIT
15:10
9
FUNCTION
Reserved
Fast Back-to-Back
Enable
P_SERR# Enable
TYPE
RO
RO
DESCRIPTION
Reserved. Returns 000000 when read.
Fast Back-to-Back Control
0:
Prohibits PI7C21P100B to initiate fast back-to-back transactions
on the primary
This bit is ignored in PCI-X mode. Reset to 0
System Error Control
0:
Disables the P_SERR# driver on the primary
1:
Enables the P_SERR# driver on the primary
Reset to 0
Wait Cycle Control
0:
Address/data stepping is disabled (primary and secondary)
This bit is ignored in PCI-X mode. Returns 0 when read.
Parity Error Response
0:
PI7C21P100B may ignore any detected parity errors and continue
normal operation
1:
PI7C21P100B must take its normal action when a parity error is
detected.
Reset to 0
VGA Palette Snoop Control
0:
Ignore VGA palette accesses on the primary
1:
Enables positive decoding response to VGA palette writes on the
primary with I/O address bits AD[9:0] equal to 3C6h, 3C8h, and
3C9h (inclusive of ISA aliases; AD[15:10] are not decoded and may
be any value.
Reset to 0
Memory Write and Invalidate Control
0:
Disables Memory Write and Invalidate transactions.
PI7C21P100B does not generate memory write and invalidate
transactions.
This bit is ignored in PCI-X mode. Returns 0 when read.
Special Cycle Control
0:
PI7C21P100B does not respond as a target to Special Cycle
transactions.
Returns 0 when read.
8
RW
7
6
Wait Cycle Control
Parity Error Response
RO
RW
5
VGA Palette Snoop
Enable
RW
4
Memory Write and
Invalidate Enable
RO
3
Special Cycle Enable
RO
Page 43 of 79
November 2005 – Revision 1.02