PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
TABLE OF CONTENTS
1
2
INTRODUCTION ................................................................................................................................ 1
SIGNAL DEFINITIONS ..................................................................................................................... 2
2.1
S
IGNAL
T
YPES
................................................................................................................................. 2
2.2
S
IGNALS
.......................................................................................................................................... 2
2.2.1
PRIMARY BUS INTERFACE SIGNALS
............................................................................ 2
2.2.3
CLOCK SIGNALS
................................................................................................................. 5
2.2.4
MISCELLANEOUS SIGNALS.............................................................................................
5
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
.......................................................... 6
2.2.6
JTAG BOUNDARY SCAN SIGNALS
.................................................................................. 6
2.2.7
POWER AND GROUND.......................................................................................................
7
2.3
PIN LIST – 208-PIN FQFP ............................................................................................................ 7
2.4
PIN LIST – 256-BALL PBGA ....................................................................................................... 9
3
PCI BUS OPERATION ..................................................................................................................... 10
3.1
TYPES OF TRANSACTIONS..................................................................................................... 10
3.2
SINGLE ADDRESS PHASE ....................................................................................................... 11
3.3
DEVICE SELECT (DEVSEL_L) GENERATION ...................................................................... 11
3.4
DATA PHASE ............................................................................................................................. 12
3.5
WRITE TRANSACTIONS .......................................................................................................... 12
3.5.1
MEMORY WRITE TRANSACTIONS................................................................................
12
3.5.2
MEMORY WRITE AND INVALIDATE
............................................................................ 13
3.5.3
DELAYED WRITE TRANSACTIONS...............................................................................
13
3.5.4
WRITE TRANSACTION ADDRESS BOUNDARIES.......................................................
14
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS.....................................................
15
3.5.6
FAST BACK-TO-BACK TRANSACTIONS
....................................................................... 15
3.6
READ TRANSACTIONS ............................................................................................................ 15
3.6.1
PREFETCHABLE READ TRANSACTIONS....................................................................
15
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS..........................................................
16
3.6.3
READ PREFETCH ADDRESS BOUNDARIES
............................................................... 16
3.6.4
DELAYED READ REQUESTS
.......................................................................................... 17
3.6.5
DELAYED READ COMPLETION WITH TARGET
........................................................ 17
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS................................................
18
3.6.7
FAST BACK-TO-BACK READ TRANSACTION
............................................................. 19
3.7
CONFIGURATION TRANSACTIONS ...................................................................................... 19
3.7.1
TYPE 0 ACCESS TO PI7C8150
......................................................................................... 19
3.7.2
TYPE 1 TO TYPE 0 CONVERSION
.................................................................................. 20
3.7.3
TYPE 1 TO TYPE 1 FORWARDING.................................................................................
21
3.7.4
SPECIAL CYCLES..............................................................................................................
22
3.8
TRANSACTION TERMINATION ............................................................................................. 23
3.8.1
MASTER TERMINATION INITIATED BY PI7C8150....................................................
24
3.8.2
MASTER ABORT RECEIVED BY PI7C8150...................................................................
24
3.8.3
TARGET TERMINATION RECEIVED BY PI7C8150
.................................................... 25
3.8.4
TARGET TERMINATION INITIATED BY PI7C8150
.................................................... 27
4
ADDRESS DECODING..................................................................................................................... 29
4.1
ADDRESS RANGES ................................................................................................................... 29
4.2
I/O ADDRESS DECODING........................................................................................................ 29
4.2.1
I/O BASE AND LIMIT ADDRESS REGISTER................................................................
30
4.2.2
ISA MODE...........................................................................................................................
31
iv
August 22, 2002 – Revision 1.02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
