PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
13
13.1
13.2
14
SUPPORTED COMMANDS......................................................................................................... 60
PRIMARY INTERFACE ............................................................................................................. 60
SECONDARY INTERFACE ....................................................................................................... 61
CONFIGURATION REGISTERS................................................................................................ 62
14.1 CONFIGURATION REGISTER ................................................................................................. 62
14.1.1
VENDOR ID REGISTER – OFFSET 00h.........................................................................
63
14.1.2
DEVICE ID REGISTER – OFFSET 00h
.......................................................................... 63
14.1.3
COMMAND REGISTER – OFFSET 04h..........................................................................
63
14.1.4
STATUS REGISTER – OFFSET 04h
................................................................................ 64
14.1.5
REVISION ID REGISTER – OFFSET 08h
...................................................................... 65
14.1.6
CLASS CODE REGISTER – OFFSET 08h.......................................................................
65
14.1.7
CACHE LINE SIZE REGISTER – OFFSET 0Ch
............................................................ 65
14.1.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
........................................... 66
14.1.9
HEADER TYPE REGISTER – OFFSET 0Ch...................................................................
66
14.1.10
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................
66
14.1.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
........................................ 66
14.1.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h....................................
66
14.1.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
.................................. 66
14.1.14
I/O BASE REGISTER – OFFSET 1Ch..........................................................................
67
14.1.15
I/O LIMIT REGISTER – OFFSET 1Ch
........................................................................ 67
14.1.16
SECONDARY STATUS REGISTER – OFFSET 1Ch...................................................
67
14.1.17
MEMORY BASE REGISTER – OFFSET 20h
.............................................................. 68
14.1.18
MEMORY LIMIT REGISTER – OFFSET 20h.............................................................
68
14.1.19
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
................................ 68
14.1.20
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h
............................ 69
14.1.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –
OFFSET 28h
....................................................................................................................................... 69
14.1.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –
OFFSET 2Ch.......................................................................................................................................
69
14.1.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
.......................... 69
14.1.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.........................
70
14.1.25
ECP POINTER REGISTER – OFFSET 34h.................................................................
70
14.1.26
INTERRUPT LINE REGISTER – OFFSET 3Ch
......................................................... 70
14.1.27
INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................
70
14.1.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
....................................................... 70
14.1.29
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h..................................
71
14.1.30
ARBITER CONTROL REGISTER – OFFSET 40h
...................................................... 72
14.1.31
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h.......................................
73
14.1.32
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
............................... 73
14.1.33
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
4Ch
.......................................................................................................................................... 73
14.1.34
UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h
........................ 74
14.1.35
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h.......................
74
14.1.36
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h
.......................................................................................................................................... 74
14.1.37
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER – OFFSET
58h
.......................................................................................................................................... 75
14.1.38
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................
75
14.1.39
GPIO DATA AND CONTROL REGISTER – OFFSET 64h
........................................ 76
14.1.40
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
................................. 76
14.1.41
P_SERR_L STATUS REGISTER – OFFSET 68h
........................................................ 77
14.1.42
PORT OPTION REGISTER – OFFSET 74h.................................................................
77
vi
August 22, 2002 – Revision 1.02
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
