PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
MS0, MS1
155, 106
B14, R16
I
Mode Selection:
Reserved for future features.
MS0
0
0
1
1
MS1
0
1
0
1
Description
RESERVED
RESERVED
Normal operation
RESERVED
MS0 should be set to 1 and MS1 should be set to 0 for
normal operation.
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
Name
GPIO[3:0]
Pin #
24, 25, 27, 28
Pin #
J3, J2, J1, K1
Type
TS
Description
General Purpose I/O Data Pins:
The 4 general-
purpose signals are programmable as either input-only
or bi-directional signals by writing the GPIO output
enable control register in the configuration space.
2.2.6
JTAG BOUNDARY SCAN SIGNALS
Name
TCK
TMS
TDO
Pin #
133
132
130
Pin #
H15
H14
H16
Type
I
I
O
Description
Test Clock.
Used to clock state information and data
into and out of the PI7C8150A during boundary scan.
Test Mode Select.
Used to control the state of the Test
Access Port controller.
Test Data Output.
When SCAN_EN_H is HIGH, it is
used (in conjunction with TCK) to shift data out of the
Test Access Port (TAP) in a serial bit stream.
Test Data Input.
When SCAN_EN_H is HIGH, it is
used (in conjunction with TCK) to shift data and
instructions into the Test Access Port (TAP) in a serial
bit stream.
Test Reset.
Active LOW signal to reset the Test Access
Port (TAP) controller into an initialized state.
TDI
129
J15
I
TRST_L
134
G15
I
2.2.7
POWER AND GROUND
Name
VDD
Pin #
1, 26, 34, 40, 51,
53, 56, 62, 69, 75,
81, 91, 97, 103,
105, 108, 114,
120, 131, 139,
145, 151, 157,
163, 170, 178,
184, 190, 196,
202, 208
Pin #
A3, C4, C15,
D7, D8, D9,
D10, E6, E7,
E8, E9, E10,
E11, F5, F12,
G4, G5, G12,
G13, H4, H5,
H12, H13, J4,
J5, J12, J13,
K4, K5, K12,
K13, L5, L12,
M6, M7, M8,
M9, M10, M11,
N7, N8, N9,
N10, P13, P15,
R3, T3
A1, A16, B1,
B2, B15, C3,
Type
P
Description
Power:
+3.3V Digital power.
VSS
12, 20, 31, 37, 48,
52, 54, 59, 66, 72,
P
Ground:
Digital ground.
Page 17 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
