PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
PI7C8150A sets the detected parity error bit in the secondary status register.
PI7C8150A sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
PI7C8150A forwards the bad parity with the data back to the initiator on the primary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
primary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8150A completes the transaction normally.
For upstream transactions, when PI7C8150A detects a read data parity error on the primary
bus, the following events occur:
PI7C8150A asserts P_PERR_L two cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
PI7C8150A sets the detected parity error bit in the primary status register.
PI7C8150A sets the data parity detected bit in the primary status register, if the
primary interface parity-error-response bit is set in the command register.
PI7C8150A forwards the bad parity with the data back to the initiator on the secondary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
secondary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8150A completes the transaction normally.
PI7C8150A returns to the initiator the data and parity that was received from the target.
When the initiator detects a parity error on this read data and is enabled to report it, the
initiator asserts PERR_L two cycles after the data transfer occurs. It is assumed that the
initiator takes responsibility for handling a parity error condition; therefore, when
PI7C8150A detects PERR_L asserted while returning read data to the initiator, PI7C8150A
does not take any further action and completes the transaction normally.
6.2.3
DELAYED WRITE TRANSACTIONS
When PI7C8150A detects a data parity error during a delayed write transaction, the
initiator drives data and data parity, and the target checks parity and conditionally asserts
PERR_L.
For delayed write transactions, a parity error can occur at the following times:
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8150A completes the delayed write transaction to the target
Page 54 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
