PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
For downstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150A has write status to return, the following events occur:
ꢀ
PI7C8150A first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if
the primary interface parity-error-response bit is set in the command register.
ꢀ
ꢀ
PI7C8150A sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150A has write status to return, the following events occur:
ꢀ
PI7C8150A first asserts S_TRDY_L and then asserts S_PERR_L two cycles later, if
the secondary interface parity-error-response bit is set in the bridge control register
(offset 3Ch).
ꢀ
ꢀ
PI7C8150A sets the secondary interface parity-error-detected bit in the secondary
status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
ꢀ
PI7C8150A asserts P_PERR_L two cycles after the data transfer, if the following are
both true:
ꢀ
ꢀ
The parity-error-response bit is set in the command register of the primary
interface.
The parity-error-response bit is set in the bridge control register of the
secondary interface.
ꢀ
PI7C8150A completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
ꢀ
PI7C8150A asserts S_PERR_L two cycles after the data transfer, if the following are
both true:
ꢀ
ꢀ
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the
secondary interface.
Page 56 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
