PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
P_SERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
1
Read
Upstream
Secondary
1
Posted Write
Downstream
Primary
0
2
(asserted)
Posted Write
Downstream
Secondary
0
3
Posted Write
Upstream
Primary
1
Posted Write
Upstream
Secondary
1
Delayed Write
Downstream
Primary
1
Delayed Write
Downstream
Secondary
1
Delayed Write
Upstream
Primary
1
Delayed Write
Upstream
Secondary
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
Primary /
Secondary Parity
Error Response
Bits
x/x
x/x
1/1
1/1
x/x
x/x
x/x
x/x
x/x
6.4
SYSTEM ERROR (SERR_L) REPORTING
PI7C8150A uses the P_SERR_L signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section 6.2.3.
Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the
following conditions apply:
For PI7C8150A to assert P_SERR_L for any reason, the SERR_L enable bit must be
set in the command register.
Whenever PI7C8150A asserts P_SERR_L, PI7C8150A must also set the signaled
system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150A asserts
P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the
SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150A
also sets the received system error bit in the secondary status register.
PI7C8150A also conditionally asserts P_SERR_L for any of the following reasons:
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
24
(default) attempts to deliver (2
24
target retries
received)
Parity error reported on target bus during posted write transaction (see previous
section)
Delayed write data discarded after 2
24
(default) attempts to deliver (2
24
target retries
received)
Delayed read data cannot be transferred from target after 2
24
(default) attempts (2
24
target retries received)
Page 62 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
