PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
P_CBE [3:0]
1111
Command
Memory Write and
Invalidate
Action
Same as Memory Read
13.2
SECONDARY INTERFACE
S_CBE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Action
Ignore
Do not claim. Ignore.
Same as Primary Interface
Same as I/O Read.
-----
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Same as Primary Interface
Same as Memory Read.
-----
-----
Ignore
I. Type 0 Configuration Write: Ignore
II. Type 1 Configuration Write (not special cycle
request):Ignore
III. Configuration Write as Special Cycle Request (device
= 1Fh, function = 7h):
1. If the target bus is the bridge’s primary bus: claim and
pass through as a Special Cycle
2. If the target bus is neither the primary bus nor is it in range
of buses defined by the bridge’s secondary and subordinate
bus registers: claim and pass through unchanged as a Type 1
Configuration Write.
3. If the target bus is not the bridge’s primary bus, but is in
range of buses defined by the bridge’s secondary and
subordinate bus registers: ignore.
Same as Memory Read
Supported
Same as Memory Read
Same as Memory Read
1100
1101
1110
1111
Memory Read
Multiple
Dual Address Cycle
Memory Read Line
Memory Write and
Invalidate
Page 76 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
