PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Bit
27
Function
Signaled Target
Abort
Received Target
Abort
Type
R/WC
Description
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
Set to 1 (by a master device) whenever transactions are terminated
with target aborts
Reset to 0
Set to 1 (by a master) when transactions are terminated with Master
Abort
Reset to 0
Set to 1 when P_SERR_L is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the primary
interface
Reset to 0
28
R/WC
29
Received Master
Abort
R/WC
30
Signaled System
Error
Detected Parity
Error
R/WC
31
R/WC
14.1.5
REVISION ID REGISTER – OFFSET 08h
Bit
7:0
Function
Revision
Type
R/O
Description
Indicates revision number of device. Hardwired to 02h
14.1.6
CLASS CODE REGISTER – OFFSET 08h
Bit
15:8
23:16
31:24
Function
Programming
Interface
Sub-Class Code
Base Class Code
Type
R/O
R/O
R/O
Description
Read as 0 to indicate no programming interfaces have been defined
for PCI-to-PCI bridges
Read as 04h to indicate device is PCI-to-PCI bridge
Read as 06h to indicate device is a bridge device
14.1.7
CACHE LINE SIZE REGISTER – OFFSET 0Ch
Bit
7:0
Function
Cache Line Size
Type
R/W
Description
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of two
are valid (only one bit can be set in this register; only 00h, 01h, 02h,
04h, 08h, and 10h are valid values).
Reset to 0
14.1.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
Bit
15:8
Function
Primary Latency
timer
Type
R/W
Description
This register sets the value for the Master Latency Timer, which
starts counting when the master asserts FRAME_L.
Reset to 0
Page 80 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
