PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
14.1.48
SLOT NUMBER REGISTER – OFFSET B0h
Bit
20:16
Function
Expansion Slot
Number
First in Chassis
Reserved
Type
R/W
Reset to 0
First in chassis
R/W
R/O
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Description
Determines expansion slot number
21
23:22
14.1.49
CHASSIS NUMBER REGISTER – OFFSET B0h
Bit
31:24
Function
Chassis Number
Register
Type
R/W
Reset to 0
Description
Chassis number register.
14.1.50
CAPABILITY ID REGISTER – OFFSET DCh
Bit
7:0
Function
Enhanced
Capabilities ID
Type
R/O
Description
Read as 01h to indicate that these are power management enhanced
capability registers.
14.1.51
NEXT ITEM POINTER REGISTER – OFFSET DCh
Bit
15:8
Function
Next Item
Pointer
Type
R/O
Description
Points to slot number register (0Bh).
14.1.52
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET
DCh
Bit
18:16
19
20
21
24:22
25
26
31:27
Function
Power
Management
Revision
PME# Clock
Auxiliary Power
Device Specific
Initialization
Reserved
D1 Power State
Support
D2 Power State
Support
PME# Support
Type
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
Description
Read as 001 to indicate the device is compliant to Revision 1.0 of
PCI Power Management Interface Specifications.
Read as 0 to indicate PI7C8150A does not support the PME# pin.
Read as 0 to indicate PI7C8150A does not support the PME# pin or
an auxiliary power source.
Read as 0 to indicate PI7C8150A does not have device specific
initialization requirements.
Read as 0
Read as 0 to indicate PI7C8150A does not support the D1 power
management state.
Read as 0 to indicate PI7C8150A does not support the D2 power
management state.
Read as 0 to indicate PI7C8150A does not support the PME# pin.
Page 96 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
