PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
14.1.53
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
Bit
Function
Type
Description
Indicates the current power state of PI7C8150A. If an
unimplemented power state is written to this register, PI7C8150A
completes the write transaction, ignores the write data, and does not
change the value of the field. Writing a value of D0 when the
previous state was D3 cause a chip reset without asserting
S_RESET_L
00: D0 state
01: not implemented
10: not implemented
11: D3 state
Reset to 0
Read as 0
Read as 0 as PI7C8150A does not support the PME# pin.
Read as 0 as the data register is not implemented.
Read as 0 as the data register is not implemented.
Read as 0 as the PME# pin is not implemented.
1:0
Power State
R/W
7:2
8
12:9
14:13
15
Reserved
PME# Enable
Data Select
Data Scale
PME status
R/O
R/O
R/O
R/O
R/O
14.1.54
CAPABILITY ID REGISTER – OFFSET E4h
Bit
Function
Type
Description
00h: Reserved.
01h: PCI Power Management (PCIPM)
02h: Accelerated Graphics Port (AGP)
03h: Vital Product Data (VPD)
7:0
Capability ID
R/O
04h: Slot Identification (SI)
05h: Message Signaled Interrupts (MSI)
06h: Compact PCI Hot Swap
07h-255h: Reserved
14.1.55
NEXT POINTER REGISTER – OFFSET E4h
Bit
15:8
Function
Next Pointer
Type
R/O
Description
End of pointer (00h)
15
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME_L signal. In a bridge, there are a number
of possibilities. Those possibilities are summarized in the table below:
Page 97 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
