Linear Photodiode Array
Imagers
Horizontal Shift Registers
Charge packets collected in the photo-
diodes as light is received are converted
to a serialized output stream through a
buried-channel, two-phase CCD shift
register that provides high charge trans-
fer efficiency at shift frequencies up to
40 MHz. The PerkinElmer 5-volt CCD
process used in this design enables
low-power, high-speed operation
with inexpensive, readily available
driver devices.
The transfer gate (Ø
TG
) controls the
movement of charge packets from the
photodiodes to the CCD shift register.
During charge integration, the voltage
controlling the transfer gate is
held in its low state to isolate the
photodiodes from the shift register.
When transfer of charge to the shift
register is desired,
ø
TG
is switched to
its high state to create a transfer
channel between the photodiodes and
the shift register. The charge transfer
sequence, detailed in Figure 4, proceeds
as follows:
After readout of a particular image line
(n), the shift register is empty of charge
and ready to accept new charge packets
from the photodiodes representing
image line (n+1). To begin the transfer
sequence, the horizontal clock pulses
(
ø
1
and
ø
2
) are stopped with
ø
1
held in
its high state, and
ø
2
in its low state.
The transfer gate voltage phase (
ø
TG
) is
then switched high to start the transfer
of charge to the shift register. Once the
transfer gate reaches its high state, the
photo gate voltage (
ø
PG
) is set high to
complete the transfer. It is recom-
mended that the photo gate voltage be
held in the high state for at least 0.1 µs
to ensure complete transfer. After this
interval, the photo gate voltage is
returned to its low state, and when
that is completed, the transfer gate
voltage is also returned to the low
state. The details of the transfer timing
are shown in Figure 3 with ranges and
tolerances in Table 1.
After transfer, the charge is transported
along the shift register by the alternate
action of two horizontal phase voltages
Figure 3: Transfer Timing Diagram
t
6
t
1
Ø
PG
t
5
t
3
t
2
Ø
TG
t
4
t
6
Ø
AB
t
8
t
7
Ø
1
V
Out
Note 1
Note 2
Notes:
1. Transition and dark pixels
2. Active pixels
Table 1. Transfer Timing Requirements
Item
Delay of
ø
TG
falling edge from
ø
PG
falling edge
Delay of
ø
TG
rising edge from end
of
ø
1
and
ø
2
clocks
Delay of
ø
AB
rising edge from
ø
PG
falling edge
Sym
t
1
Min
5 ns
Typ
20 ns
Max
-
t
2
t
3
t
4
t
5
t
6
t
7
t
8
0 ns
5 ns
100 ns
100 ns
10 ns
0 ns
-
10 ns
5 ns
500 ns
400 ns
20 ns
-
750 ns
1
-
-
-
-
-
-
-
ø
TG
pulse width
ø
PG
pulse width
Rise/fall time
Integration time
ø
AB
pulse width
Note 1: 750ns is the typical time to fully reset the photodiode.
Figure 4: Readout Timing Waveforms
t
1
Ø
1
t
2
Ø
2
t
6
t
4
t
5
Ø
RG
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DSP-101 01H - 7/2002W Page 3
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