Linear Photodiode Array
Imagers
Horizontal Shift Registers (cont.)
Table 2. Readout Timing Requirements
Item
Sym
t
1
t
2
t
4
t
5
t
6
Min
25 ns
-
-
5 ns
0 ns
Typ
-
5 ns
5 ns
-
-
Max
-
-
-
-
-
ø
1
and
ø
2
. While the two-phase CCD
shift register architecture allows
relaxed timing tolerances over those
required in three- or four-phase designs,
optimum charge transfer efficiency
and lowest power dissipation is
obtained when the overlap of the two-
phase CCD clocks occurs around the
50% transition level. Additionally, the
phase difference between signals
ø
1
and
ø
2
should be maintained near
180° and the duty cycle of both signals
should be set near 50% to prevent loss
of full-well charge storage capacity
and charge transfer efficiency. Readout
timing details are shown in Figure 4
with ranges and tolerances in Table 2.
ø
1
,
ø
2
clock period
ø
1
,
ø
2
rise/fall time
ø
RG
rise/fall time
ø
RG
clock - high duration
Delay of
ø
1
high - low
transition from
ø
RG
low*
Note: The cross over point for
ø
1
and
ø
2
clock transitions should occur within the 10 - 90% level of the clock amplitude.
Table 3. Imager Performance (Typical)
Pixel count
512 elements (RL0512P)
1024 elements (RL1024P)
2048 elements (RL2048P)
Pixel size
Exposure control
Horizontal clocking
Number of outputs
Dynamic range
1
Readout noise (rms)
amplifier
reset transistor
total noise without CDS
Saturation exposure
2
Noise equivalent exposure
2
Amplifier sensitivity
Saturation output voltage
Saturation charge capacity
Charge transfer efficiency
Peak responsivity
PRNU match across array
Dead pixels
Lag
Spectral response range
Data rate (per output)
Notes:
1. Defined as Q
sat
/rms noise (total).
2. For illumination at 750 nm.
14 µm x 14 µm
yes
2
Ø
(5V clock amplitude)
1
2500:1
25 electrons
55 electrons
60 electrons
24 nJ/cm
2
9.6 pJ/cm
2
4 µV/electrons
600 mv
150,000 electrons
0.99995
25V/µJ/cm
2
±10%
0
< 1%
250 nm - 1000 nm
40 MHz
Timing Requirements
In high-speed applications, fast
waveform transitions allow maximum
settling time of the output signal.
However, it is generally advisable to
use the slowest rise and fall times
consistent with required video
performance because fast edges tend
to introduce more transition noise
into the video waveform. When the
highest speeds are required, careful
smoothing of the waveform transitions
may improve the balance between
speed and video quality.
Output Amplifier
Charge emerging from the last stage
of the shift register is converted to a
voltage signal by a charge integrator
and video amplifier. The integrator, a
capacitor created by a floating diffusion,
is initially set to a DC reference volt-
age (V
RD
), by setting the reset transistor
voltage (
ø
RG
) to its high state. To read
out the charge,
ø
RG
is pulsed low
turning the reset transistor off and
isolating the integrator from V
RD
. The
next time
ø
1
goes low, the charge
packet is transferred to the integrator
where it generates a voltage propor-
tional to the packet size. The reset
transistor voltage,
ø
RG
, must reach
its low state prior to the high-to-low
transition of
ø
1
. An apparent clipping
of the video signal will result if this
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