PLL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
0
0
0
1
1
1
1
1
1
1
SEL2
0
1
1
0
0
0
1
1
1
1
SEL1
1
1
1
0
1
1
0
0
1
1
SEL0
1
0
1
1
0
1
0
1
0
1
Selected Multiplier
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
Note:
SEL0 is not available (always “1”) for PLL502-35 and PLL502-38 in 3x3mm package
PIN DESCRIPTIONS PLL502-35 and PLL502-38 (see next page of PLL502-37/-39)
Name
XIN
XOUT
OE
VCON
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
TSSOP
Pin number
2
3
6
7
8,9,10,14
11
13
16
15
5
4
1, 12
3x3mm QFN
Pin number
12
13
16
1
2,3,4,8,11
5
7
Not available
9
15
14
6,10
Type
I
I
I
I
P
O
O
I
I
I
I
P
Description
Crystal input. See Crystal Specification on page 4.
Crystal output. See Crystal Specification on page 4.
Output enable pin (see OE logic state table on page 1).
Voltage Control input.
Ground.
True output PECL
Complementary output PECL.
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
+3.3V power supply.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/19/06 Page 2
PLL [ PHASELINK CORPORATION ]
