PLL521-23
Low Phase Noise PECL VCXO (100MHz to 200MHz)
PACKAGE
PIN ASSIGNMENT AND DESCRIPTION
OSCOFFSEL
GNDOSC
VCON
XIN
XOUT
OECTRL
1
2
16
15
VDDOSC
BUFZSEL
OESEL
VDDANA
VDDBUF
QBAR
Q
GND
PLL521-23
3
4
5
6
7
8
14
13
12
11
10
9
DNC
GND
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
OSCOFFSEL
GNDOSC
VCON
XIN
XOUT
OECTRL
DNC
GND
GND
Q
QBAR
VDDBUF
VDDANA
OESEL
BUFZSEL
VDDOSC
Description
Oscillator Off Selection input pad. When low, turns off the oscillator when output is
disabled. When high (default), oscillator running when output is disabled.
Internal pull-up
GND connection for oscillator circuitry.
Control Voltage input. Use this pin to change the output frequency by varying the applied
Control Voltage.
Crystal oscillator input pin.
Crystal oscillator output pin.
OE input pad. See table on page 1.
Do Not Connect.
Ground connection.
Ground connection.
PECL Output.
PECL complementary output.
VDD connection for output buffer circuitry.
VDDBUF should be separately decoupled from other VDDs whenever possible.
VDD connection for analog circuitry.
VDDANA should be separately decoupled from other VDDs whenever possible.
Selector input to choose the OE control logic. See table on page 1.
Output impedance selector
VDD connection for oscillator circuitry.
VDDOSC should be separately decoupled from other VDDs whenever possible.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/19/05 Page 3
PLL [ PHASELINK CORPORATION ]
