(Preliminary)
PL580-68/69
320-640MHz Low Phase Noise VCXO
4. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
Output Clock
Duty Cycle
Short Circuit
Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS
320MHz<Fout<640MHz
MIN.
TYP.
MAX.
90/70
UNITS
mA
V
%
mA
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
2.97
45
45
45
50
50
50
±50
3.63
55
55
55
5. Jitter Specifications
PARAMETERS
Integrated jitter RMS
Period jitter RMS
Period jitter Peak-to-
Peak
CONDITIONS
Integrated 12 kHz to 20 MHz
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
FREQUENCY
320.0MHz
622.08MHz
320.0MHz
622.08MHz
320.0MHz
622.08MHz
MIN.
TYP.
0.4
0.4
3
6
25
40
MAX.
0.5
0.6
5
8
30
50
UNITS
ps
ps
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise
2
relative to
carrier (typical)
FREQ.
320.0MHz
622.08MHz
@10Hz
-59
-48
@100Hz
-86
-80
@1kHz
-116
-108
@10kHz
-129
-118
@100kHz
-124
-114
@1M
-140
-131
@10M
-148
-138
UNITS
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 5
PLL [ PHASELINK CORPORATION ]
