(Preliminary)
PL580-68/69
320-640MHz Low Phase Noise VCXO
10. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
Ω
to (V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
MAX.
V
DD
– 1.620
UNITS
V
V
11. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
0.2
0.2
TYP.
0.3
0.3
MAX.
0.45
0.45
UNITS
ns
ns
PECL Levels Test Circuit
OUT
VDD
OUT
PECL Output Skew
50Ω
2.0V
50%
50Ω
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 7
PLL [ PHASELINK CORPORATION ]
