(Preliminary)
PL580-35/37/38/39
38MHz-320MHz Low Phase Noise VCXO
4. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
Output Clock
Duty Cycle
Short Circuit
Current
Note:
CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS/CMOS
38MHz<Fout<100MHz
100MHz<Fout<320MHz
MIN.
TYP.
MAX.
65/45/30
80/60/40
UNITS
mA
V
%
mA
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
2.97
45
45
45
50
50
50
±50
3.63
55
55
55
5. Jitter Specifications
PARAMETERS
Integrated jitter RMS
CONDITIONS
Integrated 12 kHz to 20 MHz
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
FREQUENCY
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
MIN.
TYP.
0.4
0.4
2.5
3
4
18
20
25
MAX.
0.5
0.5
4
5
7
30
30
35
UNITS
ps
Period jitter RMS
ps
Period jitter Peak-to-
Peak
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise
relative to
carrier (typical)
FREQ.
77.76MHz
155.52MHz
311.04MHz
@10Hz
-66
-62
-59
@100Hz
-96
-92
-86
@1kHz
-124
-120
-116
@10kHz
-134
-132
-129
@100kHz
-132
-128
-124
@1M
-145
-144
-140
@10M
-149
-150
-148
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V.
7. CMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
SYMBOL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
20%-80% with 50Ω Load
MIN.
30
30
TYP.
MAX.
UNITS
mA
mA
0.7
0.3
ns
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/14/06 Page 5