(Preliminary)
PL611s-27
1.8V to 3.3V PicoPLL
TM
Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
T
S
10
-65
-40
150
85
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
260
UNITS
V
V
V
°C
Year
°C
°C
-
0.5
-
0.5
-
0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ V
DD
=3.3V
Input (FIN) Frequency
@ V
DD
=2.5V
@ V
DD
=1.8V
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
Output Frequency
@ V
DD
=2.5V
@ V
DD
=1.8V
Settling Time
Output Enable Time
Output Rise Time
Output Fall Time
Duty Cycle
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
V
DD
/2
45
1.2
1.2
50
70
0.9
0.1
1
CONDITIONS
MIN.
TYP.
MAX.
200
166
133
V
DD
V
DD
125
90
65
2
10
2
1.7
1.7
55
UNITS
MHz
Vpp
V
pp
MHz
MHz
MHz
ms
ns
ms
ns
ns
%
ps
Period Jitter,Pk-to-Pk*
With capacitive decoupling between V
DD
and
(measured from 10,000 samples) GND.
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/25/07 Page 4
PLL [ PHASELINK CORPORATION ]
