(Preliminary)
PL611s-28
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK[0:1]
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
•
•
•
OE - input
PDB - input
FSEL – input
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
Pin Assignment
SOT SC70 DFN
Pin # Pin# Pin#
Type
Description
This programmable I/O pin can be configured as an Output Enable
(OE) input, Power Down (PDB) input, On-the-Fly Frequency Switching
Selector (FSEL)input or CLK1 clock output. This pin has an internal
60K pull up resistor (OE, PDB & FSEL Only).
OE, PDB,
FSEL, CLK1
1
2
2
I/O
The OE and PDB features can be programmed to allow the output to
float (Hi Z), or to operate in the ‘Active low’ mode.
State
0
1 (default)
GND
XIN, FIN
XOUT
VDD
CLK0
2
3
4
5
6
1
3
4
5
6
3
1
6
5
4
P
I
O
P
O
GND connection
Crystal or Reference input pin
Crystal Output pin
Do Not Connect (DNC ) when FIN is present
VDD connection
Programmable Clock Output
OE
Disable CLK
Normal mode
PDB
Power Down Mode
Normal mode
FSEL
Frequency ‘2’
Frequency ‘1’
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 3/9/07 Page 2
PLL [ PHASELINK CORPORATION ]
