(Preliminary)
PL611s-28
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-28 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-28 accepts a fundamental input crystal of 10MHz to 50MHz or
reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 125MHz. This flexible
design allows the PL611s-28 to deliver any PLL generated frequency, F
REF
(Crystal or Ref Clk) frequency or F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-28 are mentioned below:
PLL Programming
The PLL in the PL611s-28 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (F
VCO
/(2*P)),
F
REF
(Crystal or Ref Clk Frequency) output, or
F
REF
/(2*P) output.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-28 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
- Reference (Crystal or Ref Clk) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
The output drive level can be programmed to Low
Drive (4mA), Standard Drive (8mA) or High Drive
(16mA) for each clock independently. The maximum
output frequency is 125MHz.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up
resistor giving a default condition of logic “1”.
The OE feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-28 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10 A of power. The PDB pin incorporates a 60k
pull up resistor giving a default condition of logic “1”.
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-28 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k pull
up resistor giving a default condition of logic “1”.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 3/9/07 Page 3
PLL [ PHASELINK CORPORATION ]
