(Preliminary)
PL611s-02
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
•
OE - input
•
PDB - input
•
FSEL - input
•
CLK1 – output
PACKAGE PIN ASSIGNMENT
Pin Assignment
Name
SOT23
Pin #
SC70
Pin#
DFN
Pin#
Type
Description
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB), On-the-Fly
Frequency Switching Selector (FSEL), or CLK1 clock output
This pin has an internal 60K pull up resistor for OE, PDB &
FSEL.
State
0
1 (default)
OE
Tri-State CLK
Normal mode
PDB
Power Down Mode
Normal mode
FSEL
Frequency ‘2’
Frequency ‘1’
OE, PDB,
FSEL, CLK1
1
2
2
I/O
GND
XIN, FIN
XOUT
VDD
CLK0
2
3
4
5
6
1
3
4
5
6
3
1
6
5
4
P
I
O
GND connection
Crystal or Reference Clock input pin
Crystal Output pin
Do Not Connect (DNC ) when FIN is present
P
O
VDD connection
Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 2
PLL [ PHASELINK CORPORATION ]
