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PL611S-02-XXXUC-R 参数 Datasheet PDF下载

PL611S-02-XXXUC-R图片预览
型号: PL611S-02-XXXUC-R
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8V - 3.3V PicoPLLTM ,世界上最小的可编程时钟 [1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock]
分类和应用: 光电二极管时钟
文件页数/大小: 8 页 / 215 K
品牌: PLL [ PHASELINK CORPORATION ]
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(Preliminary)
PL611s-02
1.8V-3.3V PicoPLL
TM
, World’s Smallest Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
260
150
85
UNITS
V
V
V
°C
Year
°C
°C
-
0.5
-
0.5
-
0.5
10
T
S
-65
-40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XIN)
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Output Frequency
Settling Time
Output Enable Time
VDD Sensitivity
Output Rise Time
Output Fall Time
CONDITIONS
Fundamental Crystal
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
Frequency vs. V
DD
+/-10%
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
MIN.
10
1
0.9
0.1
TYP.
MAX.
50
200
166
133
V
DD
V
DD
200
166
133
2
10
2
2
1.7
1.7
55
UNITS
MHz
MHz
V
pp
V
pp
MHz
MHz
MHz
ms
ns
ms
ppm
ns
ns
%
ps
-2
1.2
1.2
45
50
70
Duty Cycle
PLL Enabled, @ V
DD
/2
Period Jitter, Pk-to-Pk*
With capacitive decoupling between V
DD
and
(measured from 10,000 samples) GND.
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/12/06 Page 4