(Preliminary)
PL611s-18
0.5kHz-125MHz MHz to KHz Programmable Clock
T M
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M=8 bit
R= 5 bit
P= 14 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured as:
•
•
•
•
•
OE - input
FSEL - input
PDB – input
CLK1 – output
Programmable CLoad
PACKAGE PIN CONFIGURATION AND ASSIGNMENT
CLK0
CLK0
PL611s-18
PL611s-18
PL611s-18
PL611s-18
1
2
3
6
5
4
1
2
3
6
5
4
VDD
OE, PDB,
FSEL, CLK1
PL611s-18
VDD
OE, PDB,
FSEL, CLK1
PL611s-18
XIN/FIN
GND
CLK0
1
2
3
6
5
4
XOUT
OE,PDB,FSEL,CLK1
GND
XIN/FIN
GND
XIN/FIN
VDD
XOUT
XOUT
SOT23-
SOT23-6L
23
mmx3 mmx1 35mm
mm)
(3.0mmx3.0mmx1.35mm)
DFN-
DFN-6L
mmx1 mmx0 mm)
(2.0mmx1.3mmx0.6mm)
SC70-
SC70-6L
70
mmx2 25mmx mm)
mmx1
(2.3mmx2.25mmx1.0mm)
Name
XIN, FIN
GND
CLK0
VDD
Pin Assignment
DFN
SC70
SOT
Pin #
Pin#
Pin#
1
2
3
4
3
2
1
6
3
2
1
6
Type
I
P
O
P
Description
Crystal or Reference input pin.
GND connection
Programmable Clock Output
VDD connection
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB), Frequency Select
input (FSEL) or CLK1 output. This pin has an internal 60K
pull up resistor on OE, PDB and FSEL.
State
0
1 (default)
OE
Tri-state CLK
Operating mode
PDB
Power Down Mode
Operating mode
FSEL
Bank 0
Bank 1
OE, PDB,
FSEL, CLK1
5
5
5
I/O
XOUT
6
4
4
O
Crystal Output pin. Do Not Connect if FIN is used.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/23/07 Page 2
PLL [ PHASELINK CORPORATION ]
