(Preliminary)
PL611s-18
0.5kHz-125MHz MHz to KHz Programmable Clock
T M
FUNCTIONAL DESCRIPTION
PL611s-18 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-18 accepts a crystal input of 10MHz to 50MHz or a reference
clock input of 1MHz to 125MHz and is capable of producing two outputs up to 125MHz. This flexible design allows
the PL611s-18 to deliver any PLL generated frequency, F
REF
(Crystal or Ref Clk) frequency or F
REF
/(2*P) to CLK0
and/or CLK1. Some of the design features of the PL611s-18 are mentioned below:
PLL Programming
The PLL in the PL611s-18 is fully programmable.
The PLL is equipped with an 5-bit input frequency
divider (R-Counter), and an 8-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 14-bit post VCO divider
(P-Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The PL611s-18 can
also be programmed to provide a second clock
output, CLK1, on the programmable I/O pin (see
OE/PDB/FSEL/CLK1 pin description below). The
output of CLK0 can be configured as the PLL output
(F
VCO
/(2*P)), F
REF
(Ref Clk Frequency) output, or
F
REF
/(2*P) output. The output drive level can be
programmed to Low Drive (4mA), Standard Drive
(8mA) or High Drive (16mA). The maximum output
frequency is 125MHz.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-18 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
F
REF
/ 2
CLK0
CLK0 / 2
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up resistor
giving a default condition of logic “1”. Pulling the OE
pin low “0” will tri-state the output buffers.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to put
the PL611s-18 into “Sleep Mode”. When activated
(logic ‘0’), PDB ‘Disables the PLL, the oscillator
circuitry, counters, and all other active circuitry and
tri-state the output buffers. In Power Down mode the
IC consumes <5 A of power. The PDB pin
incorporates a 60k pull up resistor giving a default
condition of logic “1”.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-18 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k pull up
resistor giving a default condition of logic “1”.
Programmable CLoad
The PL611s-18 is equipped with programmable S-
Caps to allow the Cload to be tuned from 8pF to
12pF.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/23/07 Page 3
PLL [ PHASELINK CORPORATION ]
