Preliminary
PLL102-109
Programmable DDR Zero Delay Clock Driver
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Storage Temperature
Maximum power dissipation at T
A
= 55
0
C in still air
SYMBOL
V
CC
V
I
V
O
T
S
PW
MIN.
MAX.
3.6
V
CC
+
0.5
V
CC
+
0.5
150
0.7
UNITS
V
V
V
°C
W
-
0.5
-
0.5
-
0.5
-65
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
2. Electrical Characteristics
PARAMETERS
Operating supply current
High Impedance output current
Input clamp voltage
Input Capacitance
Output Capacitance
High level output voltage
Low level output voltage
Output differential-pair crossing
voltage
SYMBOL
I
DD2.5
I
DDPD
I
OZ
V
IK
C
IN
C
OUT
V
OH
V
OL
V
OC
CONDITIONS
CL = 0 pF (Fclk=100Mhz)
CL = 0 pF
VDD=2.7V, V
OUT
=VDD or GND
I
in
= -18mA
V
I
= VDD or GND
V
O
= VDD or GND
VDD = Min to Max, I
OH
= -1mA
VDD = 2.3V, I
OH
= -12mA
VDD = Min to Max, I
OL
= 1mA
VDD = 2.3V, I
OL
= 12mA
MIN.
TYP.
250
MAX.
100
±10
-1.2
UNITS
mA
uA
uA
V
pF
pF
V
V
2
3
VDD-0.1
1.7
0.1
0.6
(VDD/2)-
0.2
(VDD/
2)+0.2
V
V
V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/26/03 Page 8
PLL [ PHASELINK CORPORATION ]
